Elaboration of invariant safety properties from fault-tree analysis

Formal verification of PLC programs using model-checking requires to elaborate previously temporal logic formulae that state in a formal way the properties that must be checked. Unfortunately temporal logic is a formalism totally unknown by automation engineers. This explains why PLC programs developers willing to verify the behavior of their programs are unable to use the existing modelchecking tools. Temporal logic formulae elaboration is a too difficult task. In order to overcome this problem and to bridge the gap between PLC programs development and model-checking, this paper proposes a methodology enabling to obtain invariant safety properties from fault-tree analysis. Fault-tree analysis is a quite popular analysis method often used in industry when designing critical systems. Hence using the results of this analysis to elaborate formal properties may contribute to increase the use of formal verification techniques.